In re Waldbaum’s Empirical Analysis

Citation profile

1 federal appellate ·

Most-quoted passages

The sentences later courts lift from this opinion, ranked by how many decisions quote each — the parts of the opinion doing the work. These counts are smaller than the citation total above because most of the 15 citing decisions cite the case generally; a passage count includes only decisions quoting that exact language verbatim.

1. “The process is carried out by taking particular advantage of two features allegedly available in at least certain prior art computers: a capability of handling what we shall call an EXAMINE instruction, and an address memory device referred to by appellant as a J-register. The EXAMINE instruction causes the computer to perform several operations. First it examines the data word being analyzed and determines whether all the bits are 0’s. If the bits are all 0’s, the computer is instructed to jump to the address of that set of instructions which governs certain final calculation steps in appellant’s process. If the word contains one or more l’s, the EXAMINE instruction requires the computer to change the least significant 1 (the 1 appearing farthest to the right in the data word) to an 0. The computer then goes on to the instruction at the next consecutive address. The J-register is a device which is used when there is a jump out of the regular order of instructions. Whenever an instruction requires the computer to go to an instruction address other than that of the next consecutive instruction, the address of the next consecutive instruction is recorded in the J-register. For example, assume that there is an EXAMINE instruction located at address number 100 in a computer, and that the address of the instruction governing the final calculations is address number 500. If the data word being analyzed is “0000” when the computer arrives at the EXAMINE instruction, the word will be”

   1 later decision quote this exact passage
   e.g. In re Waldbaum

2. “1. In the data processor of a processor-controlled telephone switching system having a register into which a bit pattern of l’s and 0’s respectively representing the busy and idle states of a plurality of telephone lines is entered, said data processor including a memory for storing data and instruction words at respective addresses; means for normally controlling the sequential execution of successively addressed instruction words; a plurality of registers; means for storing memory data words in said registers; means for performing logical operations on data words in said registers, said logical operations performing means including means for comparing the contents of predetermined ones of said plurality of registers; and means responsive to the execution of a predetermined instruction word for examining the data word contained in a predetermined first one of said registers, changing the rightmost 1 in said first register to a 0 if said register contains at least one 1, controlling a transfer to the instruction word at a spec ified address in said data processor memory if said first register contains all 0’s, and storing in a predetermined second one of said registers the address of the following instruction word if said transfer is made; a method of operating said data processor to count the number of busy ones of said telephone lines represented in said register comprising the steps of: (1) controlling said storing means to store a memory data word whose number of l’s must”

   1 later decision quote this exact passage
   e.g. In re Waldbaum

3. “Conditions for patentability; novelty and loss of right to patent,”

   1 later decision quote this exact passage
   e.g. Diamond v. Diehr